Build the virtual platforms that turn imec's CPU architectures into runnable systems — before silicon. Compute System Architecture (CSA) is imec's center of excellence for hardware-software-technology co-design of future compute systems. We work in close collaboration with imec's expertise centers in applications, technology, circuits, and design to innovate and pathfind next-generation compute architectures across AI, HPC, automotive, space, and other domains.

CSA operates across six imec centers — Belgium, the Netherlands, Germany, the UK, the USA, and Qatar. This position is based primarily in Leuven, Belgium. We are looking for a SystemC / TLM-2. 0 Modeling Engineer to join the Platform, Prototypes and Physical-Aware Design (P3D) group, focusing on the CPU subsystem of imec's RISC-V-based compute platforms. You will develop SystemC TLM-2.

0 models of CPU cores, caches, memory hierarchy, and the surrounding interconnect — enabling architectural exploration, early software enablement, and pre-silicon performance analysis. Your models are the bridge between architecture and implementation: they let our architects evaluate design choices before committing to RTL, they let software teams start porting and tuning long before silicon is back, and they feed directly into the validation infrastructure that surrounds imec's prototype demonstrators — the silicon vehicles for imec's CMOS 2.

0 vision of functionally partitioned, 3D-integrated compute systems beyond what monolithic SoCs can deliver. What you will do Develop SystemC TLM-2. 0 models of the CPU subsystem — cores, caches, memory controllers, on-chip interconnect — at both loosely-timed (LT) and approximately-timed (AT) abstraction levels. Assemble and maintain virtual platforms that integrate these models with peripheral and system IP, enabling full-system simulation and early software bring-up.

Drive architectural exploration studies in close collaboration with SoC and chiplet architects: micro-architectural what-ifs, partitioning trade-offs, memory hierarchy sweeps, and chiplet interconnect dimensioning for CMOS 2. 0 systems. Define and run pre-silicon performance analysis flows — workload characterization, bottleneck identification, and PPA-relevant trade-off studies. Support hybrid RTL/TLM co-simulation environments to validate model fidelity against RTL implementations and to accelerate RTL verification with TLM-driven stimulus.

Collaborate with the RTL design and verification teams to align model behaviour with implementation and to feed insights back into the architecture loop. Document model intent, assumptions, and known limitations clearly enough that architects, designers, and software engineers can rely on the model with confidence. This is a temporary contract of two years, with the possibility to extend the contract.